With the development of technology, instruction-set simulator (ISS) is an indispensable tool for system level design. A hardware designer is able to perform the exploration and/or verification by an instruction-set simulator before the realization of the design. As a result, it is able to decrease the non-recurring engineering cost (NRE cost) in product development. A software designer can test a program on an instruction-set simulator instead of running it on real target machines, and hence the turnaround time can be reduced.
After several years of development, the performance of the traditional instruction-set simulator integrated into a single core machine is nearly optimum (fast and accurate). However, as the evolution of semiconductor manufacturing processes, two or more processors can be encapsulated in a single chip. Traditional single-core systems have been gradually substituted by multi-core systems. In order to maximize multi-core efficiency, more and more applications or programs are developed by using parallel programming model; however, the instruction-set simulator of a traditional single core system cannot manage the different cores synchronously so that simulations by different cores are not executed efficiently.
In a multi-core system, a plurality of programs is simultaneously and synchronously performed. So far, multi-core instruction-set simulation (MCISS) is designed for the programs on multi-core systems. Generally, multi-core instruction-set simulation can be established by a plurality of instruction-set simulators; however, it might result in that the instruction-set simulators randomly being arranged to the idle host core.
Refer to FIG. 1A and FIG. 1B respectively showing that the simulation time and the asynchronous target time for performing a four-core instruction-set simulator by host core 1 and host core 2. Simulation time means that the time for performing the instruction-set simulators by a host core, and target time means that the actual time for the simulated programs performed in the target. In this example, four instruction-set simulators are performed by two host cores so that each instruction-set simulator is switched to execute between two host cores and this is named context switch. If the above simulation programs start at the same time, as shown in FIG. 1B, the target time of each of the target cores is asynchronous. It may result in that the correct interaction between target programs cannot be simulated, and the problems such as race condition or deadlock cannot be revealed. Using traditional lock-step approach enables the instruction-set simulators to be synchronized in each clock tick (as shown in FIG. 1C) for the purpose of solving the above problem. As shown in FIG. 1D, it enables the target times of all simulation programs to be synchronized. The time points needing to be synchronized are named “sync point”, and each clock tick starts is a sync point. The instruction-set simulators need to stop at each sync point for the purpose of performing synchronization. Therefore, lock-step approach incurs overhead in synchronization.
Current multi-core instruction-set simulators involve a tradeoff between simulation speed and accuracy. Consequently, how to rapidly and accurately perform multi-core instruction-set simulation is a crucial role for efficient development. The present invention is directed to a method for multi-core instruction-set simulation, and it enables to perform an instruction-set simulation more rapidly and accurately by means of identifying the correlation among the processors.